The invention relates to a cell array having memory cells arranged in a semiconductor substrate to form cell rows. Each cell has a cell capacitor for storing an electrical charge that characterizes a data content of the memory cell and a cell transistor for selection of the memory cell. Word line trenches are arranged between the cell rows. The cell capacitor is provided in a lower region of a hole trench introduced from a substrate surface of the semiconductor substrate with an inner electrode arranged in the hole trench. The cell transistor is formed in an upper region of the hole trench and has an upper source/drain region, which adjoins the substrate surface and is near the surface, a lower source/drain region, which is connected to the inner electrode of the cell capacitor, and a channel region, which separates the two source/drain regions from one another and is insulated by a gate dielectric from a gate electrode provided in the word line trenches.
The invention furthermore relates to methods for fabricating a cell array and a semiconductor memory device.
Memory cells of dynamic random access memories in each comprise a cell capacitor and a cell transistor. An electrical charge is stored on a storage electrode of the cell capacitor during operation of the memory cell, the value of said charge corresponding to a respective binary data content of the memory cell. Via the cell transistor, the storage electrode is connected to a data line (also called bit line hereinafter) for the purpose of changing or reading out the data content. The cell transistor is a field-effect transistor, the gate electrode of which is connected to a word line by means of which the memory cell is addressed. A first source/drain region of the cell transistor is connected to the bit line and a second source/drain region is connected to the storage electrode of the cell capacitor. By means of a suitable potential at the gate electrode, a conductive channel is formed in a channel or body region between the two source/drain regions, via which channel the storage electrode is connected to the bit line when writing to and reading from the memory cell.
The cell capacitors are provided above or below a transistor plane formed by the cell transistors. In the case of memory cells having cell capacitors formed as hole trench capacitors or trench capacitors, the cell capacitors are formed below the transistor plane in a manner oriented to hole trenches introduced into a semiconductor substrate. The storage electrode is usually provided as an inner electrode within the hole trench and insulated by a capacitor dielectric from an outer electrode formed as a doped region in the semiconductor substrate enveloping the hole trench.
In the case of memory cells embodied in a technology with a minimum feature size of greater than 110 nm, the cell transistors are usually shaped in planar fashion in a manner oriented to a substrate surface of the semiconductor substrate (PTC, planar transistor cell). The source/drain regions of planar cell transistors are provided next to one another below the substrate surface in a manner separated from one another by the channel region. The conductive channel between the two source/drain regions, which can be controlled by the potential at the gate electrode, is essentially formed parallel to the substrate surface.
As a result of progressive reduction of the minimum feature size, it is generally endeavored to increase the performance of DRAMs and to reduce the fabrication costs per memory cell. In the case of memory cells having planar cell transistors, smaller feature sizes lead to shorter channel lengths of the channel formed between the two source/drain regions. In the case of minimum feature sizes of less than 110 nm, a shortening of the channel length corresponding to a miniaturization of the minimum feature size leads to more than proportional difficulties in connection with a lower memory voltage that is then necessary and in the realization of a doping profile of the cell transistor.
Therefore, it is known to orient the cell transistors vertically with respect to the substrate surface in order to decouple the channel length of the cell transistors from the minimum horizontal feature size which can be achieved by the lithographic method respectively used. The two source/drain regions and the channel region lying in between are arranged one above the other. In a vertical memory cell or a memory cell having a vertical cell transistor (VTC, vertical transistor cell), the channel is principally formed in a direction perpendicular to the transistor plane.
Usually, for forming the first source/drain region connected to the bit line, the semiconductor substrate is doped in a region near the surface below the substrate surface by means of an ion implantation that is unmasked in the cell array. The second source/drain region connected to the storage electrode of the cell capacitor is formed by outdiffusion of a dopant from a material introduced into the hole trench at least temporarily through a contact window (buried strap window) in the wall of the hole trench in a section of the semiconductor substrate adjoining the contact window. The buried strap diffusion region has a high dopant concentration in the region of the contact window, said dopant concentration decreasing in the vertical and horizontal directions. If the distance between two memory cells that are adjacent in a cell row is larger than the buried strap diffusion region including a space charge zone formed in their boundary region, then the channel region is connected to a connection structure which, below the buried strap diffusion regions, connects the channel regions of cell transistors arranged to form a cell array to one another with high impedance. A high-impedance connection with a resistivity resulting in the order of magnitude of the intrinsic conduction of the material of the semiconductor substrate generally suffices for avoiding floating body effects during operation of the memory cell. The floating body effect means, for instance, that charge carriers are accumulated in the channel region and a leakage current that discharges the storage electrode is established via a parasitic bipolar transistor structure that is consequently built up.
The gate electrode is provided in a manner corresponding to a region of the hole trench above the cell capacitor in word line trenches between the memory cells arranged in rows (double gate transistor) or both in the word line trenches and in the hole trench (surrounded gate transistor) and is insulated from the channel region by a gate dielectric.
An overlap between the gate electrode and a weakly doped section of the lower source/drain region is advantageous. By contrast, an overlap between the gate electrode and heavily doped sections of the lower source/drain region results in an increased gate/drain capacitance CGD, which reduces a switching speed of the cell transistor and thus increases an access time of the DRAM. Moreover, a leakage current path between the buried strap diffusion region and the gate electrode contributes a significant proportion of the total leakage current of the memory cell. A high leakage current disadvantageously increases the access time and the power consumption of the DRAM by virtue of the higher frequency of the refresh cycles that is then required. Furthermore, a high doping in the overlap region results in high local field strengths in the region of the gate dielectric, which impair the reliability thereof.